Embedded PCB

An embedded PCB is a circuit board with electronic components (such as chips, resistors, and capacitors) directly embedded in its inner layers, reducing size and improving performance.

Embedded PCBs can bury some components to reduce space occupation and shorten signal paths; components on ordinary PCBs are mostly surface-mounted.

Suitable for scenarios with high requirements for size and performance, such as smartphones, wearable devices, vehicle radars, and aerospace equipment.

Requirement analysis → schematic design → layout planning (including embedded components) → routing design (focus on signal integrity) → design rule check → board file output.

Consider dielectric constant, loss factor, and thermal expansion coefficient. For high-frequency applications, choose low-dielectric-constant and low-loss materials; for high thermal stability, choose materials with low thermal expansion coefficients.

Layout components by functional modules to shorten signal paths; disperse heat-generating components for heat dissipation; place sensitive components away from noise sources; consider process feasibility.

Resistors are made by adding resistive materials to the dielectric layer; capacitors use high-dielectric materials coated on copper foil or substrates; inductors are realized through spiral coils between layers.

Ensure reliable electrical connections, consider heat dissipation, testability, and maintainability, and follow the design guidelines of chip manufacturers.

Plan power and ground layers according to power consumption, ensure the integrity of the power plane, reduce internal resistance and voltage drop, and provide a stable power supply.

Control trace length, set trace width and spacing reasonably to reduce crosstalk, match impedance for high-speed signals, and reduce the impact of via parasitic parameters.

Dependent on materials and routing design, it can reach several Gbps or higher with proper design, such as over 10 Gbps in high-end communication devices.

Use formulas like the microstrip line formula (Z0 = (87/√(εr+1.41))×ln(5.98H/(0.8W+T))) or stripline formulas, or use design software for calculation.

Affected by material loss (dielectric/conductor loss), trace length, signal frequency, number of vias, and impedance mismatch.

Separate analog and digital circuit layouts, shield sensitive signals, ensure the integrity of power and ground planes, use filter circuits, and optimize traces to reduce loop area.

Set up large grounding planes, increase grounding vias, shorten grounding paths, and choose single-point/multi-point/hybrid grounding according to frequency.

Analyze parameters such as power network impedance, voltage drop, and current distribution through simulation software to evaluate impacts and optimize.

Strong anti-interference ability, suppress common-mode interference, improve transmission rate and reliability, and facilitate high-density routing.

Maintain length matching (difference ≤ 10% of the transmission distance corresponding to the signal rise edge), uniform trace width and spacing, control impedance (e.g., 100Ω), and avoid crosstalk.

Minimize via size, increase anti-pad, add grounding vias around, and control the aspect ratio (≤6).

Perform signal integrity, power integrity, and EMI simulation analyses, and test prototypes (e.g., using network analyzers and oscilloscopes).

Determined by component height, number of layers, mechanical strength, and application scenarios, such as 0.5-1.5mm for mobile phone PCBs and 1.6-3.2mm for industrial equipment.

Consider assembly with other components, mechanical strength, heat dissipation space, and the impact of component embedding on mechanical performance.

Reasonably layout heat-generating components, add heat dissipation channels (e.g., heat holes, copper foil), select high thermal conductivity materials, add heat dissipation devices if necessary, and optimize via thermal simulation.

Common methods include screw fixing, clip fixing, and welding fixing, suitable for high-maintenance, convenient-installation, and high-stability scenarios, respectively.

Improve mechanical strength by increasing board thickness or adding stiffeners, evenly distribute weight, use shock-absorbing materials for buffering, and reinforce key components.

Match the device casing, avoid sharp edges, consider production processes (e.g., cutting, stamping), and design plug-in guiding structures.

Apply three-proofing paint, use waterproof connectors, perform sealing treatment, and avoid placing key components in water/dust-prone areas during layout.

High temperatures may cause board expansion and component parameter drift; low temperatures may make materials brittle. Industrial-grade PCBs work at -40℃~85℃, with more stringent military-grade requirements.

Analyze deformation and stress distribution through mechanical stress simulation, and conduct impact, vibration tests, and long-term aging tests.

Different materials have different mechanical strengths and thermal expansion coefficients. For example, FR-4 has good comprehensive performance but a relatively high thermal expansion coefficient, while polyimide materials offer better thermal stability and mechanical strength.

Embedded PCBs require additional processes for component embedding, such as interlayer structure fabrication and more precise lamination, with higher requirements for drilling and plating accuracy.

Including lamination, micro-via processing (aperture ≤50μm), component embedding, and surface treatment (e.g., gold plating, tin spraying).

Specify precise tolerances in design, use high-precision equipment (such as CNC drilling machines), and conduct strict dimensional inspections and process adjustments in each procedure.

Inspect raw materials (boards, components), monitor lamination/drilling/plating parameters, use X-ray and flying probe tests to detect internal connections and electrical performance, and conduct full inspection of finished products.

Lamination bubbles/delamination, drilling misalignment/uneven aperture, poor component connection/short circuit, poor surface treatment, dimensional deviation, etc.

Optimize lamination temperature, pressure, and time parameters, pre-treat boards to remove moisture and impurities, and use vacuum lamination to expel air.

Use high-precision drilling equipment to control parameters, perform micro-etching on hole walls to improve copper plating adhesion, and detect quality through metallographic sectioning.

Screen and test components before embedding, optimize embedding processes to ensure firm connections, and conduct comprehensive electrical tests and reliability experiments after manufacturing.

Affected by material cost (high-performance materials are more expensive), process complexity (e.g., micro-vias, component embedding), production quantity, and inspection cost.

Investigate technical strength (equipment, processes), quality control systems, production cases, customer reviews, quotes, and delivery times.

Including visual inspection, electrical testing (multimeter, oscilloscope, network analyzer), functional testing, X-ray inspection, flying probe testing, etc.

Use an ICT device's bed-of-nails to contact test points and detect component electrical parameters, short circuits, open circuits, parameter deviations, etc. Test points need to be reserved in the design.

Simulate the actual working environment, comprehensively test functions, follow the order of basic to complex tests, and record and analyze anomalies.

Use the JTAG interface to operate the chip's internal boundary scan cells, detect pin states and inter-chip connections, and identify open and short circuit faults.

First observe the appearance (burned components, cracked solder joints), then perform electrical tests to narrow down the fault range, analyze possible links based on the schematic, and use the substitution method to determine the fault point.

Relatively high, as components are in inner layers. It requires carefully removing upper layers to expose the fault point, re-laminating to restore integrity after maintenance, and avoiding impacts on other circuits.

Use high-precision tools like micro-spot welding equipment and precision tweezers. Plan the maintenance scheme in advance and use localized heating to control temperature.

Conduct electrical tests (signal integrity, power integrity), functional tests, and reliability tests (aging, vibration).

Develop test plans, fault diagnosis procedures, maintenance operation specifications, and quality verification processes.

Testing equipment: multimeter, oscilloscope, network analyzer, etc. Maintenance equipment: micro-spot welding equipment, hot air gun, etc.

Consider resistance accuracy, power rating, and temperature coefficient. Select resistors based on circuit requirements.

Used for filtering, decoupling, energy storage, signal coupling, etc.

Determine based on operating frequency, inductance, and current capacity. For power filtering, consider ripple and load current.

Consider performance, power consumption, package type, reliability, and manufacturer support.

Match electrical parameters and physical dimensions during design. Select components compatible with board materials and processes, and conduct simulation verification.

For passive components, control temperature and time to prevent cold soldering. For active components, use high-precision equipment (e.g., reflow soldering) to ensure reliable connections and prevent thermal damage.

Estimate lifespan through accelerated aging tests, manufacturer data, and long-term monitoring of actual failure data.

Resistance: value drift/open circuit. Capacitor: leakage/short circuit. Inductor: inductance change/winding short. Chip: functional failure/pin faults.

Store by category with moisture and ESD protection. Maintain an inventory system to record information, conduct regular sampling, and control stock levels reasonably.

Increase trace spacing (≥3×width), use ground isolation, optimize routing topology, and match impedance.

Introduce parasitic parameters, possibly causing loss and delay at high frequencies. Vias for signals above 10GHz should have a diameter <0.3mm.

Add ESD protection devices (e.g., TVS diodes), set up ESD discharge paths, and keep key signal traces ≥2mm from board edges.

Use X-ray to inspect internal solder joints. Joint height should be 0.4-0.6mm, with void rate ≤15%.

ENIG for high-frequency and precision soldering. OSP for low cost (validity 6-8 months). Immersion tin for wave soldering.

Properly layout shield covers with grounding impedance <0.1Ω. Use layered power and ground planes with tight coupling.

Via diameter 0.3-0.5mm, spacing ≤1mm, ≥100 vias/cm² to ensure heat dissipation efficiency.

DDR4 data lines: length tolerance ±5mil. PCIe differential pairs: ±2mil.

Add decoupling capacitors (0.1μF for high frequency, 10μF for low frequency). Keep power/ground layer spacing <0.1mm.

IPC standard: ≤0.7% for lead-free processes, ≤0.5% in BGA areas.

Use dynamic voltage scaling, power down idle modules, and select low-IQ chips (e.g., TI MSP430 series).

Reduce signal loss and parasitic parameters, increase routing density. Cost 20%-30% higher than through-hole vias.

Use CAM350 or Altium DFM tools to check minimum trace width/spacing (≥6mil), aspect ratio (≤8:1), etc.

Common methods: three-proofing paint (0.1-0.3mm thickness), nano-coating (<1μm), potting compound (harsh environments).

Use fan-out design to reduce BGA routing pressure. 4-layer boards suit 80% of regular needs; ≥6 layers for high-speed designs.

Check pad cleanliness, solder paste thickness (0.12-0.15mm), and reflow temperature (peak 235-245℃).

Use a 500V megohmmeter. Insulation resistance should be ≥100MΩ at ≤60% humidity.

Use termination resistors (e.g., DDR ODT function) and impedance tapering. Ensure impedance variation <10%.

1oz copper (35μm): ~1A/mm trace width. 2oz: ~1.5A/mm (temperature rise <10℃).

Black aids heat dissipation but is hard to inspect. Green is most common. White has high reflectivity (≈80%).

Typical diameter: 0.4-0.8mm. Pitch: 0.5-1.0mm. 0.5mm pitch requires 0201 components.

Use simulation software like ANSYS, based on CTE differences (e.g., FR-4 15ppm/℃, copper 17ppm/℃).

Use multi-stage filtering (π-type circuits). Power traces ≥20mil width to reduce path impedance.

Diameter ≥0.6mm, spacing ≥1.27mm. Surface finish ENIG, no solder mask coverage.

Single-ended signal loop area <1cm². Differential signal loop area <0.1cm² to reduce EMI.

Use SI9000 to calculate impedance, control tolerance ±10%. Apply termination matching and topology optimization.

Outline: ±0.1mm. Hole diameter: ±0.05mm. V-Cut depth: 1/3-2/3 of board thickness.

Use serpentine length-matched traces with ground shielding. Keep away from high-speed data lines and avoid layer crossing.

Conduct accelerated aging tests (85℃/85%RH, 1000h) and vibration tests (5-500Hz, 2G acceleration).

Pad size 0.1-0.2mm larger than component leads. SMD pad width 1.2-1.5× lead width.

Increase thermal copper area, use thermal adhesive (≥1W/mK), and open thermal vias under power components.

According to IEC 61000-4-2: contact discharge ±8kV, air discharge ±15kV, with normal functionality.

Typical thickness 15-25μm. Must fully cover copper to prevent short circuits from exposed copper.

Combine interactive and auto-routing. Set routing priorities, with critical signals routed first.

Preheat: 120-150℃ (60-90s). Reflow: 217-230℃ (40-60s). Cooling rate: 3-6℃/s.

Single-point or multi-point grounding. Multi-point for high-frequency circuits (>10MHz), with grounding resistance <5Ω.

Consider current capacity, contact resistance (<50mΩ), mating cycles (≥500), and mechanical strength.

Observe solder joints via Metallographic section (metallographic sectioning), detect surface defects with AOI, analyze element composition with XRF.

Spacing 5mil, impedance 100±10Ω, length difference <5mil, avoid cross-talk