Thick copper PCB

It refers to printed circuit boards with copper foil thickness ≥3oz (105μm), used in high-power power supplies, automotive electronics, etc.

Common specifications include 3oz, 4oz, 5oz, 6oz, with a maximum of 20oz.

Manufacturing cost is 30%-80% higher due to difficult etching, long electroplating time, and high scrap rate.

For 3oz copper foil, conventional is 8mil/8mil, and special processes can achieve 5mil/5mil.

It requires long-term deposition to ensure copper layer uniformity. The hole copper thickness needs to reach 25-75μm, and thickness differences between hole openings and walls are prone to occur.

Normally 0.8-1.2, which can be increased to above 1.5 by step etching or laser forming.

Increase heat dissipation vias (aperture ≥0.4mm), use metal-based thermal conductive materials, and design large-area copper foil layers.

For 1oz copper foil, the current-carrying capacity of single-sided wiring at a 10℃ temperature rise is about 1A/mm, and 3oz can be increased to 2.5-3A/mm.

The thicker the copper foil, the worse the flexibility. Bending is not recommended for above 6oz, and the minimum bending radius for 3oz is ≥5mm.

Line width margin ≥20%, minimum aperture ≥0.3mm, hole copper thickness ≥25μm, and increase the density of test points.

The rotation speed is 20%-30% lower than that of ordinary PCB (about 60,000-80,000 revolutions per minute), and the feed rate is 0.02-0.04mm/rev.

ENIG is suitable for high-frequency signals. OSP has low cost but weak oxidation resistance. Hard gold plating is suitable for high-plugging connectors.

At the 10GHz frequency band, the signal loss of 6oz copper foil is about 1.5dB/inch higher than that of 1oz.

Symmetrical copper foil design, lamination temperature 180-200℃, pressure 100-150psi, cooling rate ≤3℃/min.

IPC standard ≤12.5μm, high-speed signals require ≤5μm, which can be improved by chemical copper deposition + electroplating filling.

Industry average is 75%-85%, and the yield for above 6oz may drop below 70%.

New energy vehicles (charging piles, inverters), industrial power supplies, server power supplies, aerospace and other fields.

Conventional 0.8-1.2mil, high-voltage applications require 1.5-2mil, which needs to cover the copper foil to prevent creepage.

Reduce special processes, unify copper foil thickness, expand batch size, and avoid too many blind/buried vias.

The treatment capacity of acidic copper plating solution is about 100-150Ah/L, and the concentrations of copper ions and chloride ions need to be analyzed regularly.

Peel strength ≥1.5N/mm (1oz), 3oz requires ≥2.5N/mm.

Use high Tg substrate (≥170℃), uniform lamination pressure, and timely remove drill debris after drilling.

Alkaline etching solution temperature 45-55℃, specific gravity 1.2-1.3, spray pressure 0.8-1.2MPa.

Vias need to be 100% covered with solder mask, and the opening size is 0.2-0.3mm larger than the aperture to prevent solder overflow.

Changes in copper foil thickness cause impedance fluctuations. It is necessary to simulate and optimize line width and dielectric thickness with a tolerance of ±5%.

Conventional process is 0.3mm, and laser drilling can reach 0.15mm but with high cost.

It needs to pass the 260℃/10s three-time tin immersion test without hole wall separation or copper foil peeling.

When the roughness Ra＞3μm, the signal loss increases by 10%-15%, and low-roughness copper foil (VLP) is required.

Adopt a mesh copper foil design, increase current shunt paths, and the line width of key paths ≥10mil.

Conventional ≥4mil, high voltage requires ≥8mil to prevent flashover breakdown.

Current density 0.8-1.2A/dm², precise control of additive concentration, and electroplating time is 2-3 times that of ordinary PCB.

Use a 3D optical measuring instrument, with warpage ≤0.7% and local deformation ≤0.1mm.

Immersion time ≤3 seconds, wetting angle <90°, which needs to be verified by a solderability test.

Optimize the panel design, reduce border waste, and adopt a stepped copper foil thickness zoning design.

Palladium ion concentration 0.02-0.05g/L, temperature 30-35℃, time 10-15 minutes to ensure uniform coverage of the hole wall.

1mil dielectric thickness can withstand about 500V, and the insulation spacing and copper foil spacing need to be designed according to the voltage level.

Storage humidity ≤40%, temperature ≤25℃, timely packaging after surface treatment, using moisture-proof bags + desiccants.

Milling cutter speed 25,000-30,000 revolutions per minute, feed rate 800-1200mm/min to prevent edge burrs.

Bake at 150-160℃ for 60-90 minutes, hardness ≥2H, and adhesion passes the cross-cut test.

The width of the divided area ≥20mil, avoid acute angles, and connect different power layers with via arrays.

Vickers hardness ≥80HV to prevent mechanical damage and wear.

DES process, potassium permanganate concentration 80-100g/L, temperature 60-70℃, time 15-20 minutes.

Use low Dk/Df dielectric materials, control copper foil roughness, and optimize ground plane continuity.

Annealing after lamination, keeping at 120-150℃ for 2-3 hours to release stress.

It needs to withstand wiping with isopropyl alcohol, flux, etc., without swelling or discoloration.

Spacing ≥20mil, avoid dense overheating, and a plum blossom layout can be adopted.

Pulsed electroplating technology, anode-to-board spacing 10-15cm, and regularly check anode solubility.

Laser drilling cost is about 3-5 times, but with higher precision and smaller aperture.

Silver immersion welding is fast, ENIG has high reliability, and OSP needs to complete welding within 72 hours.

Select a substrate with a CTE similar to that of copper foil (such as high Tg FR-4 with a CTE of about 14ppm/℃) to reduce thermal stress

IPC standard requires ≤10 pores/cm², and high-reliability applications require ≤5 pores/cm², which can be improved by through-hole electroplating.

Pad diameter = hole diameter + 0.6mm (conventional), and an increase of 0.1-0.2mm is required in thick copper cases to compensate for etching deviation.

Black solder resist has strong heat absorption, with a surface temperature 3-5℃ higher than white solder resist, but has little impact on overall heat dissipation.

Nickel layer thickness 3-5μm, gold layer thickness 0.05-0.1μm, plating solution pH 4.8-5.2, temperature 85-90℃.

Chemical micro-etching process is used, with the micro-etching amount controlled at 0.5-1μm, or mechanical grinding treatment.

Conventional test voltage is 1000V AC/1 minute, and high-voltage applications require an increase to 2000-5000V AC.

Under 3oz copper foil, the single-sided wiring density is recommended to be ≤15cm²/100cm², and multi-layer boards need to balance signal integrity and current-carrying capacity.

The elongation rate should be ≥20% to ensure no fracture under mechanical stress.

±50μm (conventional), and high-speed boards need to be improved to ±25μm, using a laser positioning system.

It needs to withstand reflow soldering at 280℃ for 5 seconds without blistering or cracking.

The 90° peel test is used to record the peel force per unit width, with the standard ≥1.5N/mm.

The ratio of blind hole depth to hole diameter (aspect ratio) ≤3:1 to prevent poor electroplating filling.

The phosphorus content in the electroless nickel plating layer should be controlled at 7%-9% to ensure corrosion resistance.

Coated milling cutters (such as TiAlN coating) are used, and the milling cutters are replaced regularly (replaced every 50-100㎡ of processing).

Control impedance continuity, reduce via Stub length, use differential signal transmission, and add a shielding layer.

±10% (conventional), and high-precision applications need to be controlled within ±5%.

Cross-cut test, and it is qualified if the 脱落 area after tape peeling is ≤5%.

Grid-shaped copper pouring is used (grid spacing ≤10mil) to balance current-carrying and signal return.

Tensile stress ≤15MPa, compressive stress ≤10MPa, to prevent copper foil deformation.

No resin residue or drilling debris, confirmed by metallographic section observation.

After aging at 85℃/85% RH for 168 hours, the color difference ΔE≤3.

A surface profiler is used to measure the Ra value, and the Ra of conventional copper foil is ≤5μm.

A single 0.5mm via can carry about 0.5-1A, and the number of vias needs to be determined according to the actual current demand.

An X-ray fluorescence spectrometer (XRF) is used to measure the thickness of the copper layer at different positions, with a deviation ≤10%.

Outline dimension tolerance ±0.1mm, angle deviation ±0.5°.

Match terminal impedance, optimize trace topology, and reduce right-angle traces and impedance discontinuities.

Slight oxidation can be treated with chemical micro-etching, and severe oxidation requires re-surface treatment.

Screen tension 25-35N/cm, squeegee pressure 3-5kg/cm, speed 30-50mm/s.

The power layer and the ground layer are adjacent, the signal layers are sandwiched in the middle, and the uniformity of the medium thickness is controlled.

A micro-Vickers hardness tester is used, with the distance between test points ≥0.5mm, and the average value is taken.

Mark point positioning is used, and the deviation is detected and compensated by an AOI device.

After 500 rubbings (500g pressure), there is no obvious wear or copper exposure.

Use buffer layer materials (such as thermal conductive adhesive films) or design stress relief slots.

Resin plugging + surface electroplating can be used, or solder paste filling and then curing.

Gas permeation method or metallographic microscope observation is used to calculate the number of pores per unit area.

Too high a speed is prone to produce burrs, and too low a speed affects efficiency, which needs to be adjusted according to the copper foil thickness.

Increase the trace spacing (≥3W rule), insert ground shield lines, and optimize the routing layer allocation.

Residual stress will cause copper foil deformation and cracking, reducing long-term reliability.

Local defects can be manually reprinted, and large-area defects need to be reprinted and cured.

The via spacing ≥20mil, the number is calculated according to the current-carrying demand, and they are symmetrically distributed.

X-ray diffraction method or stress ring test is used to quantify the internal stress value.

High roughness will cause uneven electroplating and increase the thickness difference of the hole copper.

After UV aging test (500 hours), there is no discoloration or chalking.

Hard gold plating has an insertion and extraction life of >1000 times, and the immersion gold process is about 50-100 times.

The cost of blind and buried vias is 30%-50% higher than that of through holes, and the cost increase is more significant in the case of thick copper.