Micro porous PCB

A printed circuit board (PCB) manufactured using laser or plasma etching technology with a hole diameter smaller than 0.15mm (the industry typically uses 0.1mm as the standard), used for high-density interconnection.

The hole diameter is more than 50% smaller than that of ordinary PCBs, the line width/spacing can reach 30μm/30μm, the wiring density is increased by 2-3 times, and it is suitable for high-frequency and high-speed signal transmission.

According to the process, they are divided into blind vias (single-sided conduction), buried vias (internal conduction), and through vias (through the entire board). The common blind via diameter range is 50-100μm.

Widely used in high-density integration scenarios such as smartphones (accounting for more than 60%), 5G base stations, server motherboards, and AI chip packaging.

It emerged after the maturity of laser drilling technology in the 1990s. The current mainstream process can achieve a 30μm hole diameter, and the minimum hole diameter record is 15μm.

The minimum hole diameter for industrial mass production can reach 50μm, and the laboratory limit is 15μm, but the cost increases exponentially with the decrease of the hole diameter.

Generally, the aspect ratio does not exceed 1:1, and special processes can reach 1:0.8. Too high an aspect ratio is likely to cause poor electroplating filling.

The recommended minimum spacing is ≥80μm to ensure the integrity of the electroless copper plating layer and reduce the risk of short circuits.

It is recommended to use alternating stacking of core boards and prepregs, with the interlayer dielectric thickness controlled at 50-75μm to ensure signal transmission quality.

It is necessary to pay attention to the parasitic capacitance of the hole (typical value <0.1pF), inductance (<1nH), and impedance continuity, and control the impedance deviation within ±5Ω.

For BGA fan-out, blind via design is preferred. Each pad corresponds to 1-2 microvias, and the fan-out line width is not less than 40μm.

Realize multi-point connection between power/ground planes through microvias, with a spacing ≤5mm, to reduce the impedance between planes.

Increase the density of heat dissipation vias (recommended ≥10 vias/cm²), with a hole diameter ≥80μm, to improve heat conduction efficiency.

The solder mask opening should be 20-30μm larger than the hole diameter on each side to prevent the solder mask ink from blocking the hole.

Adopt a build-up process to increase the number of wiring layers, and use blind and buried vias instead of through vias, which can increase the wiring density by more than 30%.

Including laser drilling (CO₂, UV laser), plasma etching, and mechanical drilling (only suitable for larger hole diameters), with laser drilling accounting for more than 80%.

CO₂ laser is suitable for hole diameters of 0.075-0.15mm with low cost; UV laser can process microvias <50μm, but the equipment cost is 3-5 times higher.

The drilling speed of CO₂ laser is about 5,000-10,000 holes per minute, and that of UV laser is about 2,000-5,000 holes per minute.

The positioning accuracy of laser drilling is ±25μm, that of mechanical drilling is ±50μm, and UV laser can achieve a high precision of ±15μm.

Nitrogen-assisted laser drilling can control the burr height within 5μm, or plasma desmearing can be used.

A through-hole electroplating process is required, with the copper plating thickness controlled at 25-35μm, and the uniformity of copper thickness in the hole ≥85%.

Deposit a 0.3-0.5μm copper layer on the insulating hole wall to provide a conductive base. The concentration of palladium ions in the activation solution needs to be controlled at 2-5ppm.

The lamination temperature is 180-210℃, the pressure is 300-500psi, and the heating rate is 1-2℃/minute to ensure uniform curing of the dielectric layer.

The vacuum degree needs to be below -95kPa. Pre-cure the prepreg to B-stage before lamination, and the bubble defect rate can be reduced to below 0.5%.

Common ones include immersion gold (thickness 0.05-0.1μm), OSP (film thickness 0.2-0.5μm), and immersion silver (0.1-0.3μm). Immersion gold has the highest reliability.

It is necessary to control the ink viscosity at 80-120Pa・s and use a vacuum plugging process to prevent ink residue in the holes, with a hole blocking rate ≤1%.

Laser cutting is used when the shape accuracy requirement is <±0.1mm. For conventional requirements, milling cutters can be used, with a cutter speed of 20,000-30,000rpm.

Including rough hole walls (roughness Ra >1.5μm), voids in holes (void ratio >5%), hole deviation (>±30μm), etc.

Plasma cleaning is used to remove drilling residues, so that the surface roughness Ra of the hole wall ≤1.0μm.

The overall yield under mature processes is about 85-92%. The smaller the hole diameter, the lower the yield. The yield of 50μm microvias is about 80%.

Including FR-4 (dielectric constant 4.2-4.5), high-speed boards (such as Rogers 4350B, Dk=3.66), BT resin, etc.

High-speed boards have a lower loss tangent (Df <0.005) and are suitable for high-frequency applications; FR-4 has low cost but large signal attenuation.

Used for interlayer bonding, with the glue content controlled at 40-50% and the fluidity at 20-30% to ensure the uniformity of the dielectric after lamination.

For the inner layer, 18μm or 35μm copper foil is recommended. For the outer layer, 18μm can be used to reduce signal loss. HDI boards often use 9μm ultra-thin copper foil.

It needs to meet the temperature resistance (no peeling at 260℃/10s), insulation resistance (>10^12Ω), and adhesion (cross-cut test level 0).

It is recommended to use RTF (reverse treatment) copper foil with a roughness Ra <0.5μm to reduce signal transmission loss.

Prefer materials with low dielectric constant (Dk <3.5) and low loss tangent (Df <0.003), such as PTFE-based boards.

They need to comply with the RoHS 2.0 directive, with halogen content (chlorine + bromine) <1500ppm and bromine <900ppm.

FR-4 base material has the lowest cost. High-speed boards cost 3-5 times that of FR-4, and BT resin is in between.

The base material needs to be stored at below 25℃ and humidity <60%. The prepreg needs to be frozen at -18℃ with a validity period of 6-12 months.

Including visual inspection, hole diameter measurement, hole copper thickness test, impedance test, and cross-section analysis.

Use a two-dimensional image measuring instrument (accuracy ±1μm) or scanning electron microscope (SEM). Automatic optical inspection (AOI) can be used for batch detection.

IPC standards require the copper thickness in the hole to be ≥20μm, and the ratio of average copper thickness to minimum copper thickness to be ≤1.5, detected by metallographic cross-section method.

Use a network analyzer with a test frequency range of 1-10GHz, and the impedance deviation should be controlled within ±10%.

It can visually observe the hole wall quality, copper layer thickness, and interlayer bonding condition, with a slicing accuracy of ±5μm.

Including thermal stress test (260℃/10 times), withstand voltage test (500V DC/1 minute), and temperature-humidity cycle test (-40℃~85℃).

Observe whether the hole wall cracks after thermal shock testing (288℃/10 times), and a crack length <50μm is qualified.

Use SEM to observe the microstructure, energy-dispersive spectroscopy (EDS) to detect elemental composition, and X-ray to detect internal defects.

Optimize the electroplating process to reduce voids in holes, strengthen the adhesion of the solder mask layer, and avoid electrochemical migration caused by environmental factors.

Under normal use conditions, it can reach 5-10 years, and harsh environments (high temperature, high humidity) will shorten it to 2-3 years.

Including SMT pasting, BGA welding, and component insertion, with an SMT pasting accuracy requirement of ±50μm.

It is necessary to control the pasting pressure at 0.5-1.0kg/cm² to prevent components from collapsing microvias, and the peak temperature of the reflow oven curve is 230-245℃.

It is necessary to precisely control the coplanarity of solder balls (<25μm), avoid solder from blocking microvias, and the welding yield is about 90-95%.

Optimize the solder paste printing thickness (100-120μm), use nitrogen-protected reflow soldering, and the oxygen content is <500ppm.

The rework temperature should be controlled below 260℃, and the time should be <90 seconds to prevent the copper layer on the hole wall from peeling off.

Suitable for microvias with a hole diameter ≥0.3mm, requiring double-wave soldering or selective wave soldering, with a solder wave height of 25-35mm.

Give priority to lead-free solder paste (SnAgCu alloy) with a melting point of 217℃, flux activity level RMA, and residue insulation resistance >10^10Ω.

Reduce the metal content of the solder paste to 90-92%, optimize the stencil opening design, and the solder bead defect rate can be reduced to below 0.1%.

Use water-based cleaning agents at a temperature of 50-60℃ for 3-5 minutes to ensure that the residue ion concentration is <1.5μg/cm².

Set the detection accuracy to ±25μm and the contrast threshold to 30-50%, which can detect more than 95% of assembly defects.

Material costs account for 40-50%, processing costs 30-40%, and inspection and packaging costs 10-20%.

Hole diameter, number of layers, surface treatment process, material type. Each 10μm reduction in the minimum hole diameter increases costs by 15-20%.

Optimize the design to reduce the number of layers, use standardized materials, and increase production batches, which can reduce costs by 10-30%.

The production cycle for conventional processes is 7-10 days, and urgent orders can be compressed to 3-5 days, but the cost increases by 20-30%.

Adopt automated production lines, optimize process flows, and increase the utilization rate of laser drilling equipment to more than 80%.

The monthly production capacity of a single production line is about 5,000-10,000㎡, depending on equipment configuration and process complexity.

The cost of small batches (<100㎡) is 40-60% higher than that of large batches (>1000㎡), mainly due to machine setup and fixed cost allocation.

Calculated comprehensively by area (yuan/㎡), number of layers, hole diameter, etc. The processing fee for a typical 8-layer 0.1mm microvia board is about 2000-3000 yuan/㎡.

Through DFM design optimization, relaxing tolerance requirements under the premise of meeting performance can reduce costs by more than 15%.

The investment in a complete production line equipment is about 10-20 million yuan, including laser drilling machines, electroplating lines, laminators, etc.

Developing towards smaller hole diameters (<30μm), higher layers (>20 layers), lower loss, and integrated packaging.

It is necessary to achieve vertical interconnection hole diameters <50μm and interlayer alignment accuracy ±10μm to meet chip stacking requirements.

Used for process parameter optimization and intelligent defect detection, which can increase yield by 5-10% and detection efficiency by 30%.

Laboratory manufacturing of 10μm hole diameters has been achieved, but mass production faces material, equipment, and cost challenges.

Achieve seamless connection between chips and PCBs through high-density interconnection, shorten signal transmission paths, and improve system performance.

Use environmentally friendly materials and processes, with heavy metal content in wastewater discharge <1ppm and energy consumption reduced by 20%.

Require low dielectric constant (Dk＜3.0), ultra-low loss (Df＜0.001) materials, and hole diameters need to optimize signal transmission structures.

It is necessary to solve the problems of hole wall cracking and copper layer peeling during bending, with a bending radius ≥3mm.

Achieve full-process monitoring and automated production through digital factories, with production efficiency increased by more than 50%.

Require extremely low loss and high stability interconnection, with hole diameters and line widths controlled at the submicron level to ensure quantum signal transmission.

Use 6-10 layer HDI boards with a hole diameter of 0.075mm to achieve high-density integration of chips, cameras, etc., accounting for 30-40% of the mobile phone motherboard cost.

Require low-loss boards (Df＜0.003), support frequency bands above 28GHz, and heat dissipation via density ≥15 vias/cm².

Need to meet high-speed interconnection of multiple processors, use back-drilling technology to eliminate stubs, and signal transmission delay <1ns.

Pass AEC-Q100 certification, temperature resistance range -40℃~125℃, and pass 1000-hour salt spray test.